This invention relates to integrated circuits, and more particularly to integrated circuits in which the switching rate is automatically controlled in response to one or more factors in order to counteract circumstances which may otherwise lead to unacceptable noise in the circuit.
Increasing sophistication in CMOS (complementary metal oxide semiconductor) fabrication techniques has opened the door to use of CMOS devices in high speed, high current drive applications. Because bipolar circuits have historically dominated these market areas, it is necessary for a CMOS device to match all bipolar capabilities in order to compete successfully. Thus it is necessary for CMOS devices to develop the same high speed with high current drive that is commonly found in bipolar TTL (transistor-transistor logic) parts.
This high speed, high drive capability can cause undesirable peripheral effects, however. Chief among these effects is noise, which comes from two sources. The first of these sources is the high speed nature of the part. An integral concomitant of high speed is the ability to rapidly slew (change the state of) the output pins from a logical 0 to a logical 1 (or from a logical 1 to a logical 0). For traditional CMOS output stages, this means swinging from very close to 0 volts to very close to 5 volts. If the slew rate doubles, the corresponding instantaneous current flowing in the output also doubles. This can be seen by examining the relation shown below: EQU T=C*dV/dt (1)
For a fixed system capacitive load C, if the slew rate dV/dt increases by a factor of two, so does the corresponding instantaneous supply current I. This current flows through system wiring and package wire bonds which behave as inductors. Inductor function is described by the relation shown below: EQU V=L*dI/dt (2)
These inductors resist rapid change in the current flowing through them. For a fixed inductance L, if dI/dt increases by a factor of two, so does the corresponding noise voltage V. Since this current is either demanded from VCC or sunk into VSS, the noise voltage is superimposed onto one or both of these two supplies. This is referred to as supply voltage spiking.
The second source of noise is the high current drive capability of the part. If all outputs simultaneously attempt to source or sink a large amount of current, this can cause a large dI/dt, even in the absence of large capacitive loads at any one pin. Since the capability to source or sink these currents is necessary, a method must be found to control the operation of the outputs so that the large currents do not cause supply voltage spiking.
It is necessary that this spiking be tightly controlled because of the extremely disruptive effects that it can have upon system operation. Supply spiking can cause loss of data, change system operation in subtle or obvious ways, and generally causes a decrease in the reliability of the system. Because the conditions that cause extreme spiking are very dependent upon the exact configuration of the system, the spiking and its deleterious consequences can be intermittent and extremely difficult for the system designer to diagnose.
The severity of the spiking is directly proportional to the number of output circuits that switch simultaneously. If a chip has a large number of high drive outputs and it is possible for all of them to switch at the same time, managing supply noise can be a very intractable problem. Good examples of such devices are high pin count erasable programmable logic devices ("EPLDs") such as those described in Hartmann et al. U.S. Pat. No. 4,609,986 and Hartmann et al. U.S. Pat. No. 4,617,479.
A simplified CMOS output driver with VCC/VSS lead frame inductances (LVCC/LVSS) and capacitive load (CL) is shown in FIG. I. (There is also typically some lead frame inductance associated with the output pin, (i.e., with CL). However, this additional inductance is ignored in the following analysis because (1) its contribution is relatively small, especially where multiple output pins are being switched simultaneously, and (2) including it would greatly complicate the equations given below.) As is customary, VCC represents the pad on the integrated circuit chip which is the source of high electrical potential (e.g., +5 volts or logic 1) for the chip, and VSS represents the pad on the integrated circuit chip which is the source of low electrical potential (e.g., 0 volts, ground, or logic 0) for the chip. When Vi (the voltage of the data input) changes from LO (logic 0) to HI (logic 1), N-channel solid-state switching device T2 starts to turn on and P-channel solid-state switching device T1 starts to turn off. The current iSINK flows through T2, the VSS pad, and the inductance LVSS. The voltage build-up vLSS at the VSS pad is given by the following equation: EQU vLSS=(LVSS)(diSINK)/(dt) (3)
The relationship between iSINK and the output terminal voltage Vo is given by the following equation: EQU iSINK=(-CL)(dVo)/(dt) (4)
The relationship between the VSS pad noise voltage vLSS and the output terminal voltage Vo is derived by substituting equation (4) into equation (3) as follows: EQU vLSS=(-LVSS)(CL)(d.sup.2 Vo)/(dt.sup.2) (5)
If multiple outputs are switched simultaneously, the VSS pad noise voltage vLSS becomes: EQU vLSS=(-N)(LVSS)(CL)(d.sup.2 Vo)/(dt.sup.2) (6)
where N is the number of outputs being switched.
At approximately the same time that T2 is turning on as described above, P-channel solid-state switching device T1 is starting to turn off. This results in VCC pad noise voltage vLCC in accordance with the following equation: EQU vLCC=(-N)(LVCC)(CL)(d.sup.2 Vo)/(dt.sup.2) (7)
where N is again the number of outputs being switched simultaneously.
When Vi changes from HI to LO, similar noise voltages (of opposite polarity) are again produced at the VSS and VCC pads.
For a given integrated circuit package and a specified output load, the values of lead frame inductance (LVCC and LVSS) for the power pins are fixed and cannot be reduced.
Other attempts have been made to control internally generated switching noise. One attempt used a technique of staggering switching of the output drivers. If calculations show that switching more than a given number of outputs results in unacceptable noise, then circuitry can be developed that limits concurrent switching. Assume, for example, that a chip has 24 outputs. Simulations show that if more than 12 outputs switch at a time, then unacceptable noise will be produced. Circuitry can be implemented that prevents half of the outputs from switching at the same time as the other half. This is an effective method for controlling noise, but it adds delay elements to the signal path.
Another attempt to control noise uses staged turn-on of the output driver devices as described in Boler et al. U.S. Pat. No. 4,638,187. If it is shown that excess noise is produced when there is a given output driver size, then the output driver may be separated into two or more smaller pieces. Circuitry is then implemented to turn on each piece separately from the others. The single large noise pulse that occurs with the large output drivers may thus be separated into smaller, more manageable noise pulses.
The disadvantage of these two previous techniques is that they add fixed delay in the signal path. If, for example, the chip is being used as a decoder, it is possible for only one output to switch at a time. The disadvantage of both staggered and staged switching methods is that they exact a permanent performance penalty to prevent a problem that, depending on system operation, may never occur. Ideally, a circuit should limit speed only when switching noise generation becomes excessive.
In view of the foregoing, it is an object of this invention to provide integrated circuits which automatically compensate for one or more circumstances which may otherwise lead to unacceptable switching noise.
It is another object of this invention to provide integrated circuits in which the switching rate is automatically reduced when a higher switching rate would result in unacceptable noise.